1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device which divides a plurality of threshold voltage distributions using determination voltages.
2. Description of the Related Art
In general, semiconductor memory devices are divided into volatile memory devices such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) and nonvolatile memory devices such as PROM (Programmable Read Only Memory), EPROM (Erasable PROM), EEPROM (Electrically EPROM), and a flash memory device. The division between the volatile memory devices and the nonvolatile memory devices mainly depends on whether or not data stored in a memory cell is maintained after a given time.
In other words, the volatile memory device may not maintain data stored in a memory cell thereof after a given time, but the nonvolatile memory device maintains data stored in a memory cell thereof even after a given time. Therefore, the volatile memory device is to perform a refresh operation to maintain data, and the volatile memory device operates without such a refresh operation. Since the characteristic of the nonvolatile memory device is suitable for low power and high integration, the nonvolatile memory device is widely used as a storage medium of portable devices.
Meanwhile, the flash memory device among the nonvolatile memory devices stores data in memory cells through a programming operation and an erasing operation. Here, the programming operation refers to an operation of storing electrons in a floating gate of a transistor forming a memory cell, and the erasing operation refers to an operation of discharging the electrons stored in the floating gate of the transistor to a substrate. The flash memory device stores data of ‘0’ or ‘1’ in the memory cell through such an operation. Furthermore, during a reading operation, the flash memory device senses the quantity of electrons stored in the floating gate and determines whether the data stored in the memory cell is ‘0’ or ‘1’ depending on the sensing result.
As described above, data of ‘0’ or ‘1’ may be stored in one memory cell. That is, one bit data is stored in one memory cell, and the memory cell is referred to as a single level cell. A method of storing one or more-bit data in one memory cell has been adopted, and the memory cell is referred to as a multi-level cell. While the single level cell uses a single threshold voltage as one determination voltage to determine whether the data stored therein is ‘0’ or ‘1’, the multi-level cell uses, for example, three or more determination voltages to determine whether the data stored therein is ‘00’, ‘01’, ‘10’, or ‘11’.
Meanwhile, a memory cell of the flash memory device has a threshold voltage in a given voltage distribution depending on the corresponding data stored therein. However, voltage distributions for multi-bit data, e.g., ‘00’, ‘01’, ‘10’, or ‘11’, may overlap each other. In this case, data outputted by a determination voltage during a read operation may differ from data which is actually stored. Therefore, the flash memory device provides various methods for correcting such an error. The methods may include a method using an error correction code (ECC). The ECC is an additional code inputted with data. The flash memory device detects and corrects error data through an error correction operation using the ECC.
With the technology development, the voltage distributions have been narrowed. However, a distance between adjacent voltage distributions has also been reduced for operations based on low power consumption. When the distance between the adjacent voltage distributions is reduced, it means that an overlapping portion between the adjacent voltage distributions increases. This means that it is highly likely that an error occurs when data are outputted. Since the number of data to be corrected by an error correction operation is limited, a method capable of utilizing an ECC is being developed.